The present invention relates to a semiconductor device; and, more particularly, to a semiconductor device having a shield line.
As well-known in the art, a semiconductor device is a semiconductor device for storing quantities of data. This semiconductor device can be largely divided into a data storage area storing data and a peripheral area for effectively accessing the data stored in the data storage area. The data storage area has a plurality of unit cells for storing a corresponding number of data bits. The peripheral area has a data output circuit for receiving the data stored in the data storage area and outputting the data externally, a data input circuit for conveying externally received data to the data storage area, and an address input circuit for receiving addresses for designating locations of data to be accessed. In addition, the peripheral area further has a mode register which stores information that enables the above circuits to operate normally. For example, the mode register stores information such as a burst length denoting the number of data bits output during a single data access, a Column Address Strobe (CAS) latency denoting a time from an input of the address to an output of corresponding data, and so on.
In the general semiconductor device, the data input circuit, the data output circuit and the address input circuit are circuits that are continuously operated during a data access operation. On the other hand, circuits such as the mode register are not operated for every data access, but are operated only when the semiconductor device sets related information during an initial operation. Therefore, once each of lines or wires associated with the mode register is designated at one level, is the level need not be varied while a data access operation is performed.
The semiconductor device employs these lines as shield lines of other lines in order to effectively arrange internal circuits and lines. However, one shortcoming is that there may be an error due to a variation of a voltage level of each line which is under the protection of the shields lines. Namely, the shield lines are influenced by level transition of the lines which are under the protection of the shields lines, thus making it possible to transition to an opposite level without maintaining an originally required level.
FIG. 1 is a diagram showing coupling capacitors between lines.
Referring to FIG. 1, there are provided a shield line S, lines A1 and A2 that are under the protection of the shield line, and coupling capacitors Cc1 and Cc2 disposed therebetween. In addition, there is a parasitic capacitor Csb between the shield line S and a substrate. When a voltage level of the lines A1 and A2 rises from a ground voltage level to a power supply voltage level, a voltage of the shield line S arranged therebetween will rise by ΔVc. At this time, the risen level affects the operation of circuits coupled to the shield line, and thus, a level of signal other than a predetermined level may be output via the shield line S. An equation shown in FIG. 1 is derived under the assumption that no charge additionally flows into the lines A1 and A2. Actually, since the semiconductor device has a driver for driving the lines A1 and A2, the variation widths of the lines A1 and A2 may be different from each other depending on the driving capability of the driver driving the lines A1 and A2 and resistance thereof.
FIG. 2 is a diagram for more particularly describing the problem caused by the coupling capacitors shown in FIG. 1.
With reference to FIG. 2, a shield line S is arranged for transferring a signal output from a signal output unit 10 to a signal input unit 20. The signal transferred through the shield line S is not intended to be varied once it is set, such as the signal required when the memory device is initially sets. Therefore, in a normal mode that allows the memory device to perform a data access operation, a level of a signal applied to the shield line S is not varied if it is set once.
It is first assumed that the shield line S is maintained at a logic low level and a signal is continuously delivered to each of the lines A1 and A2 adjacent to the shield line S. When the signal to each of the lines A1 and A2 rises from the ground voltage level to the power supply voltage, the voltage level of the shield line S rises by ΔVb by the coupling effect. At this time, if the voltage level by the risen voltage ΔVb is higher than a threshold voltage of MOS transistors arranged in the signal input unit 20, the MOS transistor MN2 is turned on. When the MOS transistor MN2 is turned on, a voltage level at a node N2 transitions from a logic high level to a logic low level. This implies that a normally set signal is changed to an improper level which may cause an error in the operation of the semiconductor device.
The above problem may also be caused when the voltage level of the shield line S is maintained at a logic high level. In this case, when the voltage level of the lines A1 and A2 drops from a logic high level to a logic low level, the voltage level of the shield line S can drop from the logic high level by ΔVb. Because of the dropped voltage by ΔVb, when the MOS transistor MP2 is turned on, the level at the node N2 can transition from the logic low level to the logic high level. This also implies that a normally set signal is changed to an improper level, which makes the semiconductor device malfunction and cause any error therein. In order to solve the above problem, the shield line can include a dummy line through which no signal is transferred, but in this case, a circuit size is increased.